1. Technical Field
This disclosure generally relates to the field of processor architecture and, more particularly, to register renaming using shadow registers in processors.
2. Description of the Related Art
In general, a processor is a device that can execute computer programs to carry out algorithmic computation, data permutation, etc. Microprocessors are a type of processor that incorporates most or all of the functions of a processor on a single integrated circuit. Superscalar microprocessors are microprocessors that can execute more than one instruction during a clock cycle by simultaneously dispatching multiple instructions to redundant execution resources, also known as functional units, in the processor. When executing instructions and micro-operations, processors typically read source operands from registers and store results or destination operands in registers. Registers are temporary storage units within the processor whose contents can be accessed more quickly than storage available elsewhere, and are typically used for holding arithmetic and other results used by the processor. A given register may contain a number of bits, e.g., 8 bits, 16 bits, or 32 bits, and is addressable by a respective register identifier, such as a register number.
The programs executed by a processor typically specify reads and writes to a limited set of registers as specified by the instruction set architecture, and this limited set of registers are known as the architectural registers. For example, a given instruction set architecture may specify 32 integer registers each 64-bit wide, and 32 floating-point registers each 64-bit wide. In such case, programs written for processors running this particular instruction set architecture will specify operations reading and writing to those 64 architectural registers.
In superscalar computing, a register renaming logic is typically used to rename, or map, architectural registers to corresponding physical registers so that more dependent instructions can be issued and executed while avoiding problems such as false data dependency. The number of physical registers is often larger than the number of architectural registers. For example, there may be twice as many physical registers as there are architectural registers in a given processor. An architectural register mapping table (ARMT) and a physical register mapping table (PRMT) are used to record the mapping relationships between the architectural registers and the physical registers. In particular, the ARMT records the physical register identifier of the physical register to which an architectural register is renamed, or mapped, to for each of the architectural registers. The PRMT records the status, operational state, and mapping relationship for each physical register of the set of physical registers.
Shadow registers are physical registers in processors that are typically used during debugging, exception, and interrupt. They provide temporary data storage upon the occurrence of a state, e.g., exception or interrupt, that changes the normal flow of execution of instructions. Traditionally, shadow registers are implemented in processors by the use of two sets of registers, or register files, with the processor using a first set of the two sets of registers during a normal state and using a second set of the two sets of registers, e.g., the shadow registers, during an abnormal state such as exception or interrupt. More specifically, when in the abnormal state, data stored in the first set of registers is copied to the second set of registers, or the shadow registers, for the processor to execute instructions using the second set of registers. When the processor returns to the normal state, data stored in the second set of registers is copied back to the first set of registers for the processor to operate on. For instance, the first set of registers may be used for renaming a number of architectural registers when the processor is in the normal state. When the processor enters the abnormal state due to exception or interrupt, the processor switches to using the second set of registers to rename those architectural registers. When the processor returns to the normal state again, it switches back to using the first set of registers to rename the architectural registers.
The switching back and forth between two sets of registers in the conventional implementation of shadow registers, however, is both time-consuming and power-consuming. In particular, time is consumed when data is copied from one set of registers to the other. Further, the operations of reading data from a source register, transmitting the data, and writing the data into destination register all consume power. Moreover, two sets of registers are needed to implement shadow registering even though only one set is used at any given time. Thus, the conventional implementation of shadow registers results in inefficient use of hardware, since one of the two sets of registers is not used at any given time.